diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs index 9c67266..ef0ceea 100644 --- a/compiler/nativeGen/X86/Instr.hs +++ b/compiler/nativeGen/X86/Instr.hs @@ -1,1036 +1,1039 @@ {-# LANGUAGE CPP, TypeFamilies #-} ----------------------------------------------------------------------------- -- -- Machine-dependent assembly language -- -- (c) The University of Glasgow 1993-2004 -- ----------------------------------------------------------------------------- module X86.Instr (Instr(..), Operand(..), PrefetchVariant(..), JumpDest, getJumpDestBlockId, canShortcut, shortcutStatics, shortcutJump, i386_insert_ffrees, allocMoreStack, maxSpillSlots, archWordSize) where #include "HsVersions.h" #include "nativeGen/NCG.h" import X86.Cond import X86.Regs import Instruction import Size import RegClass import Reg import TargetReg import BlockId import CodeGen.Platform import Cmm import FastString import FastBool import Outputable import Platform import BasicTypes (Alignment) import CLabel import DynFlags import UniqSet import Unique import UniqSupply import Control.Monad import Data.Maybe (fromMaybe) -- Size of an x86/x86_64 memory address, in bytes. -- archWordSize :: Bool -> Size archWordSize is32Bit | is32Bit = II32 | otherwise = II64 -- | Instruction instance for x86 instruction set. instance Instruction Instr where regUsageOfInstr = x86_regUsageOfInstr patchRegsOfInstr = x86_patchRegsOfInstr isJumpishInstr = x86_isJumpishInstr jumpDestsOfInstr = x86_jumpDestsOfInstr patchJumpInstr = x86_patchJumpInstr mkSpillInstr = x86_mkSpillInstr mkLoadInstr = x86_mkLoadInstr takeDeltaInstr = x86_takeDeltaInstr isMetaInstr = x86_isMetaInstr mkRegRegMoveInstr = x86_mkRegRegMoveInstr takeRegRegMoveInstr = x86_takeRegRegMoveInstr mkJumpInstr = x86_mkJumpInstr mkStackAllocInstr = x86_mkStackAllocInstr mkStackDeallocInstr = x86_mkStackDeallocInstr -- ----------------------------------------------------------------------------- -- Intel x86 instructions {- Intel, in their infinite wisdom, selected a stack model for floating point registers on x86. That might have made sense back in 1979 -- nowadays we can see it for the nonsense it really is. A stack model fits poorly with the existing nativeGen infrastructure, which assumes flat integer and FP register sets. Prior to this commit, nativeGen could not generate correct x86 FP code -- to do so would have meant somehow working the register-stack paradigm into the register allocator and spiller, which sounds very difficult. We have decided to cheat, and go for a simple fix which requires no infrastructure modifications, at the expense of generating ropey but correct FP code. All notions of the x86 FP stack and its insns have been removed. Instead, we pretend (to the instruction selector and register allocator) that x86 has six floating point registers, %fake0 .. %fake5, which can be used in the usual flat manner. We further claim that x86 has floating point instructions very similar to SPARC and Alpha, that is, a simple 3-operand register-register arrangement. Code generation and register allocation proceed on this basis. When we come to print out the final assembly, our convenient fiction is converted to dismal reality. Each fake instruction is independently converted to a series of real x86 instructions. %fake0 .. %fake5 are mapped to %st(0) .. %st(5). To do reg-reg arithmetic operations, the two operands are pushed onto the top of the FP stack, the operation done, and the result copied back into the relevant register. There are only six %fake registers because 2 are needed for the translation, and x86 has 8 in total. The translation is inefficient but is simple and it works. A cleverer translation would handle a sequence of insns, simulating the FP stack contents, would not impose a fixed mapping from %fake to %st regs, and hopefully could avoid most of the redundant reg-reg moves of the current translation. We might as well make use of whatever unique FP facilities Intel have chosen to bless us with (let's not be churlish, after all). Hence GLDZ and GLD1. Bwahahahahahahaha! -} {- Note [x86 Floating point precision] Intel's internal floating point registers are by default 80 bit extended precision. This means that all operations done on values in registers are done at 80 bits, and unless the intermediate values are truncated to the appropriate size (32 or 64 bits) by storing in memory, calculations in registers will give different results from calculations which pass intermediate values in memory (eg. via function calls). One solution is to set the FPU into 64 bit precision mode. Some OSs do this (eg. FreeBSD) and some don't (eg. Linux). The problem here is that this will only affect 64-bit precision arithmetic; 32-bit calculations will still be done at 64-bit precision in registers. So it doesn't solve the whole problem. There's also the issue of what the C library is expecting in terms of precision. It seems to be the case that glibc on Linux expects the FPU to be set to 80 bit precision, so setting it to 64 bit could have unexpected effects. Changing the default could have undesirable effects on other 3rd-party library code too, so the right thing would be to save/restore the FPU control word across Haskell code if we were to do this. gcc's -ffloat-store gives consistent results by always storing the results of floating-point calculations in memory, which works for both 32 and 64-bit precision. However, it only affects the values of user-declared floating point variables in C, not intermediate results. GHC in -fvia-C mode uses -ffloat-store (see the -fexcess-precision flag). Another problem is how to spill floating point registers in the register allocator. Should we spill the whole 80 bits, or just 64? On an OS which is set to 64 bit precision, spilling 64 is fine. On Linux, spilling 64 bits will round the results of some operations. This is what gcc does. Spilling at 80 bits requires taking up a full 128 bit slot (so we get alignment). We spill at 80-bits and ignore the alignment problems. In the future [edit: now available in GHC 7.0.1, with the -msse2 flag], we'll use the SSE registers for floating point. This requires a CPU that supports SSE2 (ordinary SSE only supports 32 bit precision float ops), which means P4 or Xeon and above. Using SSE will solve all these problems, because the SSE registers use fixed 32 bit or 64 bit precision. --SDM 1/2003 -} data Instr -- comment pseudo-op = COMMENT FastString -- some static data spat out during code -- generation. Will be extracted before -- pretty-printing. | LDATA Section (Alignment, CmmStatics) -- start a new basic block. Useful during -- codegen, removed later. Preceding -- instruction should be a jump, as per the -- invariants for a BasicBlock (see Cmm). | NEWBLOCK BlockId -- specify current stack offset for -- benefit of subsequent passes | DELTA Int -- Moves. | MOV Size Operand Operand + | CMOV Cond Size Operand Reg | MOVZxL Size Operand Operand -- size is the size of operand 1 | MOVSxL Size Operand Operand -- size is the size of operand 1 -- x86_64 note: plain mov into a 32-bit register always zero-extends -- into the 64-bit reg, in contrast to the 8 and 16-bit movs which -- don't affect the high bits of the register. -- Load effective address (also a very useful three-operand add instruction :-) | LEA Size Operand Operand -- Int Arithmetic. | ADD Size Operand Operand | ADC Size Operand Operand | SUB Size Operand Operand | MUL Size Operand Operand | MUL2 Size Operand -- %edx:%eax = operand * %rax | IMUL Size Operand Operand -- signed int mul | IMUL2 Size Operand -- %edx:%eax = operand * %eax | DIV Size Operand -- eax := eax:edx/op, edx := eax:edx%op | IDIV Size Operand -- ditto, but signed -- Int Arithmetic, where the effects on the condition register -- are important. Used in specialized sequences such as MO_Add2. -- Do not rewrite these instructions to "equivalent" ones that -- have different effect on the condition register! (See #9013.) | ADD_CC Size Operand Operand -- Simple bit-twiddling. | AND Size Operand Operand | OR Size Operand Operand | XOR Size Operand Operand | NOT Size Operand | NEGI Size Operand -- NEG instruction (name clash with Cond) | BSWAP Size Reg -- Shifts (amount may be immediate or %cl only) | SHL Size Operand{-amount-} Operand | SAR Size Operand{-amount-} Operand | SHR Size Operand{-amount-} Operand | BT Size Imm Operand | NOP -- x86 Float Arithmetic. -- Note that we cheat by treating G{ABS,MOV,NEG} of doubles -- as single instructions right up until we spit them out. -- all the 3-operand fake fp insns are src1 src2 dst -- and furthermore are constrained to be fp regs only. -- IMPORTANT: keep is_G_insn up to date with any changes here | GMOV Reg Reg -- src(fpreg), dst(fpreg) | GLD Size AddrMode Reg -- src, dst(fpreg) | GST Size Reg AddrMode -- src(fpreg), dst | GLDZ Reg -- dst(fpreg) | GLD1 Reg -- dst(fpreg) | GFTOI Reg Reg -- src(fpreg), dst(intreg) | GDTOI Reg Reg -- src(fpreg), dst(intreg) | GITOF Reg Reg -- src(intreg), dst(fpreg) | GITOD Reg Reg -- src(intreg), dst(fpreg) | GDTOF Reg Reg -- src(fpreg), dst(fpreg) | GADD Size Reg Reg Reg -- src1, src2, dst | GDIV Size Reg Reg Reg -- src1, src2, dst | GSUB Size Reg Reg Reg -- src1, src2, dst | GMUL Size Reg Reg Reg -- src1, src2, dst -- FP compare. Cond must be `elem` [EQQ, NE, LE, LTT, GE, GTT] -- Compare src1 with src2; set the Zero flag iff the numbers are -- comparable and the comparison is True. Subsequent code must -- test the %eflags zero flag regardless of the supplied Cond. | GCMP Cond Reg Reg -- src1, src2 | GABS Size Reg Reg -- src, dst | GNEG Size Reg Reg -- src, dst | GSQRT Size Reg Reg -- src, dst | GSIN Size CLabel CLabel Reg Reg -- src, dst | GCOS Size CLabel CLabel Reg Reg -- src, dst | GTAN Size CLabel CLabel Reg Reg -- src, dst | GFREE -- do ffree on all x86 regs; an ugly hack -- SSE2 floating point: we use a restricted set of the available SSE2 -- instructions for floating-point. -- use MOV for moving (either movss or movsd (movlpd better?)) | CVTSS2SD Reg Reg -- F32 to F64 | CVTSD2SS Reg Reg -- F64 to F32 | CVTTSS2SIQ Size Operand Reg -- F32 to I32/I64 (with truncation) | CVTTSD2SIQ Size Operand Reg -- F64 to I32/I64 (with truncation) | CVTSI2SS Size Operand Reg -- I32/I64 to F32 | CVTSI2SD Size Operand Reg -- I32/I64 to F64 -- use ADD & SUB for arithmetic. In both cases, operands -- are Operand Reg. -- SSE2 floating-point division: | FDIV Size Operand Operand -- divisor, dividend(dst) -- use CMP for comparisons. ucomiss and ucomisd instructions -- compare single/double prec floating point respectively. | SQRT Size Operand Reg -- src, dst -- Comparison | TEST Size Operand Operand | CMP Size Operand Operand | SETCC Cond Operand -- Stack Operations. | PUSH Size Operand | POP Size Operand -- both unused (SDM): -- | PUSHA -- | POPA -- Jumping around. | JMP Operand [Reg] -- including live Regs at the call | JXX Cond BlockId -- includes unconditional branches | JXX_GBL Cond Imm -- non-local version of JXX -- Table jump | JMP_TBL Operand -- Address to jump to [Maybe BlockId] -- Blocks in the jump table Section -- Data section jump table should be put in CLabel -- Label of jump table | CALL (Either Imm Reg) [Reg] -- Other things. | CLTD Size -- sign extend %eax into %edx:%eax | FETCHGOT Reg -- pseudo-insn for ELF position-independent code -- pretty-prints as -- call 1f -- 1: popl %reg -- addl __GLOBAL_OFFSET_TABLE__+.-1b, %reg | FETCHPC Reg -- pseudo-insn for Darwin position-independent code -- pretty-prints as -- call 1f -- 1: popl %reg -- bit counting instructions | POPCNT Size Operand Reg -- [SSE4.2] count number of bits set to 1 | BSF Size Operand Reg -- bit scan forward | BSR Size Operand Reg -- bit scan reverse -- prefetch | PREFETCH PrefetchVariant Size Operand -- prefetch Variant, addr size, address to prefetch -- variant can be NTA, Lvl0, Lvl1, or Lvl2 | LOCK Instr -- lock prefix | XADD Size Operand Operand -- src (r), dst (r/m) | CMPXCHG Size Operand Operand -- src (r), dst (r/m), eax implicit | MFENCE data PrefetchVariant = NTA | Lvl0 | Lvl1 | Lvl2 data Operand = OpReg Reg -- register | OpImm Imm -- immediate value | OpAddr AddrMode -- memory reference -- | Returns which registers are read and written as a (read, written) -- pair. x86_regUsageOfInstr :: Platform -> Instr -> RegUsage x86_regUsageOfInstr platform instr = case instr of MOV _ src dst -> usageRW src dst + CMOV _ _ src dst -> mkRU (use_R src [dst]) [dst] MOVZxL _ src dst -> usageRW src dst MOVSxL _ src dst -> usageRW src dst LEA _ src dst -> usageRW src dst ADD _ src dst -> usageRM src dst ADC _ src dst -> usageRM src dst SUB _ src dst -> usageRM src dst IMUL _ src dst -> usageRM src dst IMUL2 _ src -> mkRU (eax:use_R src []) [eax,edx] MUL _ src dst -> usageRM src dst MUL2 _ src -> mkRU (eax:use_R src []) [eax,edx] DIV _ op -> mkRU (eax:edx:use_R op []) [eax,edx] IDIV _ op -> mkRU (eax:edx:use_R op []) [eax,edx] ADD_CC _ src dst -> usageRM src dst AND _ src dst -> usageRM src dst OR _ src dst -> usageRM src dst XOR _ (OpReg src) (OpReg dst) | src == dst -> mkRU [] [dst] XOR _ src dst -> usageRM src dst NOT _ op -> usageM op BSWAP _ reg -> mkRU [reg] [reg] NEGI _ op -> usageM op SHL _ imm dst -> usageRM imm dst SAR _ imm dst -> usageRM imm dst SHR _ imm dst -> usageRM imm dst BT _ _ src -> mkRUR (use_R src []) PUSH _ op -> mkRUR (use_R op []) POP _ op -> mkRU [] (def_W op) TEST _ src dst -> mkRUR (use_R src $! use_R dst []) CMP _ src dst -> mkRUR (use_R src $! use_R dst []) SETCC _ op -> mkRU [] (def_W op) JXX _ _ -> mkRU [] [] JXX_GBL _ _ -> mkRU [] [] JMP op regs -> mkRUR (use_R op regs) JMP_TBL op _ _ _ -> mkRUR (use_R op []) CALL (Left _) params -> mkRU params (callClobberedRegs platform) CALL (Right reg) params -> mkRU (reg:params) (callClobberedRegs platform) CLTD _ -> mkRU [eax] [edx] NOP -> mkRU [] [] GMOV src dst -> mkRU [src] [dst] GLD _ src dst -> mkRU (use_EA src []) [dst] GST _ src dst -> mkRUR (src : use_EA dst []) GLDZ dst -> mkRU [] [dst] GLD1 dst -> mkRU [] [dst] GFTOI src dst -> mkRU [src] [dst] GDTOI src dst -> mkRU [src] [dst] GITOF src dst -> mkRU [src] [dst] GITOD src dst -> mkRU [src] [dst] GDTOF src dst -> mkRU [src] [dst] GADD _ s1 s2 dst -> mkRU [s1,s2] [dst] GSUB _ s1 s2 dst -> mkRU [s1,s2] [dst] GMUL _ s1 s2 dst -> mkRU [s1,s2] [dst] GDIV _ s1 s2 dst -> mkRU [s1,s2] [dst] GCMP _ src1 src2 -> mkRUR [src1,src2] GABS _ src dst -> mkRU [src] [dst] GNEG _ src dst -> mkRU [src] [dst] GSQRT _ src dst -> mkRU [src] [dst] GSIN _ _ _ src dst -> mkRU [src] [dst] GCOS _ _ _ src dst -> mkRU [src] [dst] GTAN _ _ _ src dst -> mkRU [src] [dst] CVTSS2SD src dst -> mkRU [src] [dst] CVTSD2SS src dst -> mkRU [src] [dst] CVTTSS2SIQ _ src dst -> mkRU (use_R src []) [dst] CVTTSD2SIQ _ src dst -> mkRU (use_R src []) [dst] CVTSI2SS _ src dst -> mkRU (use_R src []) [dst] CVTSI2SD _ src dst -> mkRU (use_R src []) [dst] FDIV _ src dst -> usageRM src dst FETCHGOT reg -> mkRU [] [reg] FETCHPC reg -> mkRU [] [reg] COMMENT _ -> noUsage DELTA _ -> noUsage POPCNT _ src dst -> mkRU (use_R src []) [dst] BSF _ src dst -> mkRU (use_R src []) [dst] BSR _ src dst -> mkRU (use_R src []) [dst] -- note: might be a better way to do this PREFETCH _ _ src -> mkRU (use_R src []) [] LOCK i -> x86_regUsageOfInstr platform i XADD _ src dst -> usageMM src dst CMPXCHG _ src dst -> usageRMM src dst (OpReg eax) MFENCE -> noUsage _other -> panic "regUsage: unrecognised instr" where -- # Definitions -- -- Written: If the operand is a register, it's written. If it's an -- address, registers mentioned in the address are read. -- -- Modified: If the operand is a register, it's both read and -- written. If it's an address, registers mentioned in the address -- are read. -- 2 operand form; first operand Read; second Written usageRW :: Operand -> Operand -> RegUsage usageRW op (OpReg reg) = mkRU (use_R op []) [reg] usageRW op (OpAddr ea) = mkRUR (use_R op $! use_EA ea []) usageRW _ _ = panic "X86.RegInfo.usageRW: no match" -- 2 operand form; first operand Read; second Modified usageRM :: Operand -> Operand -> RegUsage usageRM op (OpReg reg) = mkRU (use_R op [reg]) [reg] usageRM op (OpAddr ea) = mkRUR (use_R op $! use_EA ea []) usageRM _ _ = panic "X86.RegInfo.usageRM: no match" -- 2 operand form; first operand Modified; second Modified usageMM :: Operand -> Operand -> RegUsage usageMM (OpReg src) (OpReg dst) = mkRU [src, dst] [src, dst] usageMM (OpReg src) (OpAddr ea) = mkRU (use_EA ea [src]) [src] usageMM _ _ = panic "X86.RegInfo.usageMM: no match" -- 3 operand form; first operand Read; second Modified; third Modified usageRMM :: Operand -> Operand -> Operand -> RegUsage usageRMM (OpReg src) (OpReg dst) (OpReg reg) = mkRU [src, dst, reg] [dst, reg] usageRMM (OpReg src) (OpAddr ea) (OpReg reg) = mkRU (use_EA ea [src, reg]) [reg] usageRMM _ _ _ = panic "X86.RegInfo.usageRMM: no match" -- 1 operand form; operand Modified usageM :: Operand -> RegUsage usageM (OpReg reg) = mkRU [reg] [reg] usageM (OpAddr ea) = mkRUR (use_EA ea []) usageM _ = panic "X86.RegInfo.usageM: no match" -- Registers defd when an operand is written. def_W (OpReg reg) = [reg] def_W (OpAddr _ ) = [] def_W _ = panic "X86.RegInfo.def_W: no match" -- Registers used when an operand is read. use_R (OpReg reg) tl = reg : tl use_R (OpImm _) tl = tl use_R (OpAddr ea) tl = use_EA ea tl -- Registers used to compute an effective address. use_EA (ImmAddr _ _) tl = tl use_EA (AddrBaseIndex base index _) tl = use_base base $! use_index index tl where use_base (EABaseReg r) tl = r : tl use_base _ tl = tl use_index EAIndexNone tl = tl use_index (EAIndex i _) tl = i : tl mkRUR src = src' `seq` RU src' [] where src' = filter (interesting platform) src mkRU src dst = src' `seq` dst' `seq` RU src' dst' where src' = filter (interesting platform) src dst' = filter (interesting platform) dst -- | Is this register interesting for the register allocator? interesting :: Platform -> Reg -> Bool interesting _ (RegVirtual _) = True interesting platform (RegReal (RealRegSingle i)) = isFastTrue (freeReg platform i) interesting _ (RegReal (RealRegPair{})) = panic "X86.interesting: no reg pairs on this arch" -- | Applies the supplied function to all registers in instructions. -- Typically used to change virtual registers to real registers. x86_patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr x86_patchRegsOfInstr instr env = case instr of MOV sz src dst -> patch2 (MOV sz) src dst + CMOV cc sz src dst -> CMOV cc sz (patchOp src) (env dst) MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst LEA sz src dst -> patch2 (LEA sz) src dst ADD sz src dst -> patch2 (ADD sz) src dst ADC sz src dst -> patch2 (ADC sz) src dst SUB sz src dst -> patch2 (SUB sz) src dst IMUL sz src dst -> patch2 (IMUL sz) src dst IMUL2 sz src -> patch1 (IMUL2 sz) src MUL sz src dst -> patch2 (MUL sz) src dst MUL2 sz src -> patch1 (MUL2 sz) src IDIV sz op -> patch1 (IDIV sz) op DIV sz op -> patch1 (DIV sz) op ADD_CC sz src dst -> patch2 (ADD_CC sz) src dst AND sz src dst -> patch2 (AND sz) src dst OR sz src dst -> patch2 (OR sz) src dst XOR sz src dst -> patch2 (XOR sz) src dst NOT sz op -> patch1 (NOT sz) op BSWAP sz reg -> BSWAP sz (env reg) NEGI sz op -> patch1 (NEGI sz) op SHL sz imm dst -> patch1 (SHL sz imm) dst SAR sz imm dst -> patch1 (SAR sz imm) dst SHR sz imm dst -> patch1 (SHR sz imm) dst BT sz imm src -> patch1 (BT sz imm) src TEST sz src dst -> patch2 (TEST sz) src dst CMP sz src dst -> patch2 (CMP sz) src dst PUSH sz op -> patch1 (PUSH sz) op POP sz op -> patch1 (POP sz) op SETCC cond op -> patch1 (SETCC cond) op JMP op regs -> JMP (patchOp op) regs JMP_TBL op ids s lbl-> JMP_TBL (patchOp op) ids s lbl GMOV src dst -> GMOV (env src) (env dst) GLD sz src dst -> GLD sz (lookupAddr src) (env dst) GST sz src dst -> GST sz (env src) (lookupAddr dst) GLDZ dst -> GLDZ (env dst) GLD1 dst -> GLD1 (env dst) GFTOI src dst -> GFTOI (env src) (env dst) GDTOI src dst -> GDTOI (env src) (env dst) GITOF src dst -> GITOF (env src) (env dst) GITOD src dst -> GITOD (env src) (env dst) GDTOF src dst -> GDTOF (env src) (env dst) GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst) GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst) GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst) GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst) GCMP sz src1 src2 -> GCMP sz (env src1) (env src2) GABS sz src dst -> GABS sz (env src) (env dst) GNEG sz src dst -> GNEG sz (env src) (env dst) GSQRT sz src dst -> GSQRT sz (env src) (env dst) GSIN sz l1 l2 src dst -> GSIN sz l1 l2 (env src) (env dst) GCOS sz l1 l2 src dst -> GCOS sz l1 l2 (env src) (env dst) GTAN sz l1 l2 src dst -> GTAN sz l1 l2 (env src) (env dst) CVTSS2SD src dst -> CVTSS2SD (env src) (env dst) CVTSD2SS src dst -> CVTSD2SS (env src) (env dst) CVTTSS2SIQ sz src dst -> CVTTSS2SIQ sz (patchOp src) (env dst) CVTTSD2SIQ sz src dst -> CVTTSD2SIQ sz (patchOp src) (env dst) CVTSI2SS sz src dst -> CVTSI2SS sz (patchOp src) (env dst) CVTSI2SD sz src dst -> CVTSI2SD sz (patchOp src) (env dst) FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst) CALL (Left _) _ -> instr CALL (Right reg) p -> CALL (Right (env reg)) p FETCHGOT reg -> FETCHGOT (env reg) FETCHPC reg -> FETCHPC (env reg) NOP -> instr COMMENT _ -> instr DELTA _ -> instr JXX _ _ -> instr JXX_GBL _ _ -> instr CLTD _ -> instr POPCNT sz src dst -> POPCNT sz (patchOp src) (env dst) BSF sz src dst -> BSF sz (patchOp src) (env dst) BSR sz src dst -> BSR sz (patchOp src) (env dst) PREFETCH lvl size src -> PREFETCH lvl size (patchOp src) LOCK i -> LOCK (x86_patchRegsOfInstr i env) XADD sz src dst -> patch2 (XADD sz) src dst CMPXCHG sz src dst -> patch2 (CMPXCHG sz) src dst MFENCE -> instr _other -> panic "patchRegs: unrecognised instr" where patch1 :: (Operand -> a) -> Operand -> a patch1 insn op = insn $! patchOp op patch2 :: (Operand -> Operand -> a) -> Operand -> Operand -> a patch2 insn src dst = (insn $! patchOp src) $! patchOp dst patchOp (OpReg reg) = OpReg $! env reg patchOp (OpImm imm) = OpImm imm patchOp (OpAddr ea) = OpAddr $! lookupAddr ea lookupAddr (ImmAddr imm off) = ImmAddr imm off lookupAddr (AddrBaseIndex base index disp) = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp where lookupBase EABaseNone = EABaseNone lookupBase EABaseRip = EABaseRip lookupBase (EABaseReg r) = EABaseReg $! env r lookupIndex EAIndexNone = EAIndexNone lookupIndex (EAIndex r i) = (EAIndex $! env r) i -------------------------------------------------------------------------------- x86_isJumpishInstr :: Instr -> Bool x86_isJumpishInstr instr = case instr of JMP{} -> True JXX{} -> True JXX_GBL{} -> True JMP_TBL{} -> True CALL{} -> True _ -> False x86_jumpDestsOfInstr :: Instr -> [BlockId] x86_jumpDestsOfInstr insn = case insn of JXX _ id -> [id] JMP_TBL _ ids _ _ -> [id | Just id <- ids] _ -> [] x86_patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr x86_patchJumpInstr insn patchF = case insn of JXX cc id -> JXX cc (patchF id) JMP_TBL op ids section lbl -> JMP_TBL op (map (fmap patchF) ids) section lbl _ -> insn -- ----------------------------------------------------------------------------- -- | Make a spill instruction. x86_mkSpillInstr :: DynFlags -> Reg -- register to spill -> Int -- current stack delta -> Int -- spill slot to use -> Instr x86_mkSpillInstr dflags reg delta slot = let off = spillSlotToOffset platform slot - delta in case targetClassOfReg platform reg of RcInteger -> MOV (archWordSize is32Bit) (OpReg reg) (OpAddr (spRel dflags off)) RcDouble -> GST FF80 reg (spRel dflags off) {- RcFloat/RcDouble -} RcDoubleSSE -> MOV FF64 (OpReg reg) (OpAddr (spRel dflags off)) _ -> panic "X86.mkSpillInstr: no match" where platform = targetPlatform dflags is32Bit = target32Bit platform -- | Make a spill reload instruction. x86_mkLoadInstr :: DynFlags -> Reg -- register to load -> Int -- current stack delta -> Int -- spill slot to use -> Instr x86_mkLoadInstr dflags reg delta slot = let off = spillSlotToOffset platform slot - delta in case targetClassOfReg platform reg of RcInteger -> MOV (archWordSize is32Bit) (OpAddr (spRel dflags off)) (OpReg reg) RcDouble -> GLD FF80 (spRel dflags off) reg {- RcFloat/RcDouble -} RcDoubleSSE -> MOV FF64 (OpAddr (spRel dflags off)) (OpReg reg) _ -> panic "X86.x86_mkLoadInstr" where platform = targetPlatform dflags is32Bit = target32Bit platform spillSlotSize :: Platform -> Int spillSlotSize dflags = if is32Bit then 12 else 8 where is32Bit = target32Bit dflags maxSpillSlots :: DynFlags -> Int maxSpillSlots dflags = ((rESERVED_C_STACK_BYTES dflags - 64) `div` spillSlotSize (targetPlatform dflags)) - 1 -- = 0 -- useful for testing allocMoreStack -- number of bytes that the stack pointer should be aligned to stackAlign :: Int stackAlign = 16 -- convert a spill slot number to a *byte* offset, with no sign: -- decide on a per arch basis whether you are spilling above or below -- the C stack pointer. spillSlotToOffset :: Platform -> Int -> Int spillSlotToOffset platform slot = 64 + spillSlotSize platform * slot -------------------------------------------------------------------------------- -- | See if this instruction is telling us the current C stack delta x86_takeDeltaInstr :: Instr -> Maybe Int x86_takeDeltaInstr instr = case instr of DELTA i -> Just i _ -> Nothing x86_isMetaInstr :: Instr -> Bool x86_isMetaInstr instr = case instr of COMMENT{} -> True LDATA{} -> True NEWBLOCK{} -> True DELTA{} -> True _ -> False -- | Make a reg-reg move instruction. -- On SPARC v8 there are no instructions to move directly between -- floating point and integer regs. If we need to do that then we -- have to go via memory. -- x86_mkRegRegMoveInstr :: Platform -> Reg -> Reg -> Instr x86_mkRegRegMoveInstr platform src dst = case targetClassOfReg platform src of RcInteger -> case platformArch platform of ArchX86 -> MOV II32 (OpReg src) (OpReg dst) ArchX86_64 -> MOV II64 (OpReg src) (OpReg dst) _ -> panic "x86_mkRegRegMoveInstr: Bad arch" RcDouble -> GMOV src dst RcDoubleSSE -> MOV FF64 (OpReg src) (OpReg dst) _ -> panic "X86.RegInfo.mkRegRegMoveInstr: no match" -- | Check whether an instruction represents a reg-reg move. -- The register allocator attempts to eliminate reg->reg moves whenever it can, -- by assigning the src and dest temporaries to the same real register. -- x86_takeRegRegMoveInstr :: Instr -> Maybe (Reg,Reg) x86_takeRegRegMoveInstr (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2) x86_takeRegRegMoveInstr _ = Nothing -- | Make an unconditional branch instruction. x86_mkJumpInstr :: BlockId -> [Instr] x86_mkJumpInstr id = [JXX ALWAYS id] x86_mkStackAllocInstr :: Platform -> Int -> Instr x86_mkStackAllocInstr platform amount = case platformArch platform of ArchX86 -> SUB II32 (OpImm (ImmInt amount)) (OpReg esp) ArchX86_64 -> SUB II64 (OpImm (ImmInt amount)) (OpReg rsp) _ -> panic "x86_mkStackAllocInstr" x86_mkStackDeallocInstr :: Platform -> Int -> Instr x86_mkStackDeallocInstr platform amount = case platformArch platform of ArchX86 -> ADD II32 (OpImm (ImmInt amount)) (OpReg esp) ArchX86_64 -> ADD II64 (OpImm (ImmInt amount)) (OpReg rsp) _ -> panic "x86_mkStackDeallocInstr" i386_insert_ffrees :: [GenBasicBlock Instr] -> [GenBasicBlock Instr] i386_insert_ffrees blocks | any (any is_G_instr) [ instrs | BasicBlock _ instrs <- blocks ] = map insertGFREEs blocks | otherwise = blocks where insertGFREEs (BasicBlock id insns) = BasicBlock id (insertBeforeNonlocalTransfers GFREE insns) insertBeforeNonlocalTransfers :: Instr -> [Instr] -> [Instr] insertBeforeNonlocalTransfers insert insns = foldr p [] insns where p insn r = case insn of CALL _ _ -> insert : insn : r JMP _ _ -> insert : insn : r JXX_GBL _ _ -> panic "insertBeforeNonlocalTransfers: cannot handle JXX_GBL" _ -> insn : r -- if you ever add a new FP insn to the fake x86 FP insn set, -- you must update this too is_G_instr :: Instr -> Bool is_G_instr instr = case instr of GMOV{} -> True GLD{} -> True GST{} -> True GLDZ{} -> True GLD1{} -> True GFTOI{} -> True GDTOI{} -> True GITOF{} -> True GITOD{} -> True GDTOF{} -> True GADD{} -> True GDIV{} -> True GSUB{} -> True GMUL{} -> True GCMP{} -> True GABS{} -> True GNEG{} -> True GSQRT{} -> True GSIN{} -> True GCOS{} -> True GTAN{} -> True GFREE -> panic "is_G_instr: GFREE (!)" _ -> False -- -- Note [extra spill slots] -- -- If the register allocator used more spill slots than we have -- pre-allocated (rESERVED_C_STACK_BYTES), then we must allocate more -- C stack space on entry and exit from this proc. Therefore we -- insert a "sub $N, %rsp" at every entry point, and an "add $N, %rsp" -- before every non-local jump. -- -- This became necessary when the new codegen started bundling entire -- functions together into one proc, because the register allocator -- assigns a different stack slot to each virtual reg within a proc. -- To avoid using so many slots we could also: -- -- - split up the proc into connected components before code generator -- -- - rename the virtual regs, so that we re-use vreg names and hence -- stack slots for non-overlapping vregs. -- -- Note that when a block is both a non-local entry point (with an -- info table) and a local branch target, we have to split it into -- two, like so: -- -- -- L: -- -- -- becomes -- -- -- L: -- subl $rsp, N -- jmp Lnew -- Lnew: -- -- -- and all branches pointing to L are retargetted to point to Lnew. -- Otherwise, we would repeat the $rsp adjustment for each branch to -- L. -- allocMoreStack :: Platform -> Int -> NatCmmDecl statics X86.Instr.Instr -> UniqSM (NatCmmDecl statics X86.Instr.Instr) allocMoreStack _ _ top@(CmmData _ _) = return top allocMoreStack platform slots proc@(CmmProc info lbl live (ListGraph code)) = do let entries = entryBlocks proc uniqs <- replicateM (length entries) getUniqueUs let delta = ((x + stackAlign - 1) `quot` stackAlign) * stackAlign -- round up where x = slots * spillSlotSize platform -- sp delta alloc = mkStackAllocInstr platform delta dealloc = mkStackDeallocInstr platform delta new_blockmap :: BlockEnv BlockId new_blockmap = mapFromList (zip entries (map mkBlockId uniqs)) insert_stack_insns (BasicBlock id insns) | Just new_blockid <- mapLookup id new_blockmap = [ BasicBlock id [alloc, JXX ALWAYS new_blockid] , BasicBlock new_blockid block' ] | otherwise = [ BasicBlock id block' ] where block' = foldr insert_dealloc [] insns insert_dealloc insn r = case insn of JMP _ _ -> dealloc : insn : r JXX_GBL _ _ -> panic "insert_dealloc: cannot handle JXX_GBL" _other -> x86_patchJumpInstr insn retarget : r where retarget b = fromMaybe b (mapLookup b new_blockmap) new_code = concatMap insert_stack_insns code -- in return (CmmProc info lbl live (ListGraph new_code)) data JumpDest = DestBlockId BlockId | DestImm Imm getJumpDestBlockId :: JumpDest -> Maybe BlockId getJumpDestBlockId (DestBlockId bid) = Just bid getJumpDestBlockId _ = Nothing canShortcut :: Instr -> Maybe JumpDest canShortcut (JXX ALWAYS id) = Just (DestBlockId id) canShortcut (JMP (OpImm imm) _) = Just (DestImm imm) canShortcut _ = Nothing -- This helper shortcuts a sequence of branches. -- The blockset helps avoid following cycles. shortcutJump :: (BlockId -> Maybe JumpDest) -> Instr -> Instr shortcutJump fn insn = shortcutJump' fn (setEmpty :: BlockSet) insn where shortcutJump' fn seen insn@(JXX cc id) = if setMember id seen then insn else case fn id of Nothing -> insn Just (DestBlockId id') -> shortcutJump' fn seen' (JXX cc id') Just (DestImm imm) -> shortcutJump' fn seen' (JXX_GBL cc imm) where seen' = setInsert id seen shortcutJump' _ _ other = other -- Here because it knows about JumpDest shortcutStatics :: (BlockId -> Maybe JumpDest) -> (Alignment, CmmStatics) -> (Alignment, CmmStatics) shortcutStatics fn (align, Statics lbl statics) = (align, Statics lbl $ map (shortcutStatic fn) statics) -- we need to get the jump tables, so apply the mapping to the entries -- of a CmmData too. shortcutLabel :: (BlockId -> Maybe JumpDest) -> CLabel -> CLabel shortcutLabel fn lab | Just uq <- maybeAsmTemp lab = shortBlockId fn emptyUniqSet (mkBlockId uq) | otherwise = lab shortcutStatic :: (BlockId -> Maybe JumpDest) -> CmmStatic -> CmmStatic shortcutStatic fn (CmmStaticLit (CmmLabel lab)) = CmmStaticLit (CmmLabel (shortcutLabel fn lab)) shortcutStatic fn (CmmStaticLit (CmmLabelDiffOff lbl1 lbl2 off)) = CmmStaticLit (CmmLabelDiffOff (shortcutLabel fn lbl1) lbl2 off) -- slightly dodgy, we're ignoring the second label, but this -- works with the way we use CmmLabelDiffOff for jump tables now. shortcutStatic _ other_static = other_static shortBlockId :: (BlockId -> Maybe JumpDest) -> UniqSet Unique -> BlockId -> CLabel shortBlockId fn seen blockid = case (elementOfUniqSet uq seen, fn blockid) of (True, _) -> mkAsmTempLabel uq (_, Nothing) -> mkAsmTempLabel uq (_, Just (DestBlockId blockid')) -> shortBlockId fn (addOneToUniqSet seen uq) blockid' (_, Just (DestImm (ImmCLbl lbl))) -> lbl (_, _other) -> panic "shortBlockId" where uq = getUnique blockid diff --git a/compiler/nativeGen/X86/Ppr.hs b/compiler/nativeGen/X86/Ppr.hs index 0aa7b9e..89bb0b0 100644 --- a/compiler/nativeGen/X86/Ppr.hs +++ b/compiler/nativeGen/X86/Ppr.hs @@ -1,1212 +1,1227 @@ {-# LANGUAGE CPP #-} ----------------------------------------------------------------------------- -- -- Pretty-printing assembly language -- -- (c) The University of Glasgow 1993-2005 -- ----------------------------------------------------------------------------- {-# OPTIONS_GHC -fno-warn-orphans #-} module X86.Ppr ( pprNatCmmDecl, pprBasicBlock, pprSectionHeader, pprData, pprInstr, pprSize, pprImm, pprDataItem, ) where #include "HsVersions.h" #include "nativeGen/NCG.h" import X86.Regs import X86.Instr import X86.Cond import Instruction import Size import Reg import PprBase import BlockId import BasicTypes (Alignment) import DynFlags import Cmm hiding (topInfoTable) import CLabel import Unique ( pprUnique, Uniquable(..) ) import Platform import FastString import Outputable import Data.Word import Data.Bits -- ----------------------------------------------------------------------------- -- Printing this stuff out pprNatCmmDecl :: NatCmmDecl (Alignment, CmmStatics) Instr -> SDoc pprNatCmmDecl (CmmData section dats) = pprSectionHeader section $$ pprDatas dats pprNatCmmDecl proc@(CmmProc top_info lbl _ (ListGraph blocks)) = case topInfoTable proc of Nothing -> case blocks of [] -> -- special case for split markers: pprLabel lbl blocks -> -- special case for code without info table: pprSectionHeader Text $$ pprLabel lbl $$ -- blocks guaranteed not null, so label needed vcat (map (pprBasicBlock top_info) blocks) $$ pprSizeDecl lbl Just (Statics info_lbl _) -> sdocWithPlatform $ \platform -> (if platformHasSubsectionsViaSymbols platform then pprSectionHeader Text $$ ppr (mkDeadStripPreventer info_lbl) <> char ':' else empty) $$ vcat (map (pprBasicBlock top_info) blocks) $$ -- above: Even the first block gets a label, because with branch-chain -- elimination, it might be the target of a goto. (if platformHasSubsectionsViaSymbols platform then -- If we are using the .subsections_via_symbols directive -- (available on recent versions of Darwin), -- we have to make sure that there is some kind of reference -- from the entry code to a label on the _top_ of of the info table, -- so that the linker will not think it is unreferenced and dead-strip -- it. That's why the label is called a DeadStripPreventer (_dsp). text "\t.long " <+> ppr info_lbl <+> char '-' <+> ppr (mkDeadStripPreventer info_lbl) else empty) $$ pprSizeDecl info_lbl -- | Output the ELF .size directive. pprSizeDecl :: CLabel -> SDoc pprSizeDecl lbl = sdocWithPlatform $ \platform -> if osElfTarget (platformOS platform) then ptext (sLit "\t.size") <+> ppr lbl <> ptext (sLit ", .-") <> ppr lbl else empty pprBasicBlock :: BlockEnv CmmStatics -> NatBasicBlock Instr -> SDoc pprBasicBlock info_env (BasicBlock blockid instrs) = maybe_infotable $$ pprLabel (mkAsmTempLabel (getUnique blockid)) $$ vcat (map pprInstr instrs) where maybe_infotable = case mapLookup blockid info_env of Nothing -> empty Just (Statics info_lbl info) -> pprSectionHeader Text $$ vcat (map pprData info) $$ pprLabel info_lbl pprDatas :: (Alignment, CmmStatics) -> SDoc pprDatas (align, (Statics lbl dats)) = vcat (pprAlign align : pprLabel lbl : map pprData dats) -- TODO: could remove if align == 1 pprData :: CmmStatic -> SDoc pprData (CmmString str) = pprASCII str pprData (CmmUninitialised bytes) = sdocWithPlatform $ \platform -> if platformOS platform == OSDarwin then ptext (sLit ".space ") <> int bytes else ptext (sLit ".skip ") <> int bytes pprData (CmmStaticLit lit) = pprDataItem lit pprGloblDecl :: CLabel -> SDoc pprGloblDecl lbl | not (externallyVisibleCLabel lbl) = empty | otherwise = ptext (sLit ".globl ") <> ppr lbl pprTypeAndSizeDecl :: CLabel -> SDoc pprTypeAndSizeDecl lbl = sdocWithPlatform $ \platform -> if osElfTarget (platformOS platform) && externallyVisibleCLabel lbl then ptext (sLit ".type ") <> ppr lbl <> ptext (sLit ", @object") else empty pprLabel :: CLabel -> SDoc pprLabel lbl = pprGloblDecl lbl $$ pprTypeAndSizeDecl lbl $$ (ppr lbl <> char ':') pprASCII :: [Word8] -> SDoc pprASCII str = vcat (map do1 str) $$ do1 0 where do1 :: Word8 -> SDoc do1 w = ptext (sLit "\t.byte\t") <> int (fromIntegral w) pprAlign :: Int -> SDoc pprAlign bytes = sdocWithPlatform $ \platform -> ptext (sLit ".align ") <> int (alignment platform) where alignment platform = if platformOS platform == OSDarwin then log2 bytes else bytes log2 :: Int -> Int -- cache the common ones log2 1 = 0 log2 2 = 1 log2 4 = 2 log2 8 = 3 log2 n = 1 + log2 (n `quot` 2) -- ----------------------------------------------------------------------------- -- pprInstr: print an 'Instr' instance Outputable Instr where ppr instr = pprInstr instr pprReg :: Size -> Reg -> SDoc pprReg s r = case r of RegReal (RealRegSingle i) -> sdocWithPlatform $ \platform -> if target32Bit platform then ppr32_reg_no s i else ppr64_reg_no s i RegReal (RealRegPair _ _) -> panic "X86.Ppr: no reg pairs on this arch" RegVirtual (VirtualRegI u) -> text "%vI_" <> pprUnique u RegVirtual (VirtualRegHi u) -> text "%vHi_" <> pprUnique u RegVirtual (VirtualRegF u) -> text "%vF_" <> pprUnique u RegVirtual (VirtualRegD u) -> text "%vD_" <> pprUnique u RegVirtual (VirtualRegSSE u) -> text "%vSSE_" <> pprUnique u where ppr32_reg_no :: Size -> Int -> SDoc ppr32_reg_no II8 = ppr32_reg_byte ppr32_reg_no II16 = ppr32_reg_word ppr32_reg_no _ = ppr32_reg_long ppr32_reg_byte i = ptext (case i of { 0 -> sLit "%al"; 1 -> sLit "%bl"; 2 -> sLit "%cl"; 3 -> sLit "%dl"; _ -> sLit "very naughty I386 byte register" }) ppr32_reg_word i = ptext (case i of { 0 -> sLit "%ax"; 1 -> sLit "%bx"; 2 -> sLit "%cx"; 3 -> sLit "%dx"; 4 -> sLit "%si"; 5 -> sLit "%di"; 6 -> sLit "%bp"; 7 -> sLit "%sp"; _ -> sLit "very naughty I386 word register" }) ppr32_reg_long i = ptext (case i of { 0 -> sLit "%eax"; 1 -> sLit "%ebx"; 2 -> sLit "%ecx"; 3 -> sLit "%edx"; 4 -> sLit "%esi"; 5 -> sLit "%edi"; 6 -> sLit "%ebp"; 7 -> sLit "%esp"; _ -> ppr_reg_float i }) ppr64_reg_no :: Size -> Int -> SDoc ppr64_reg_no II8 = ppr64_reg_byte ppr64_reg_no II16 = ppr64_reg_word ppr64_reg_no II32 = ppr64_reg_long ppr64_reg_no _ = ppr64_reg_quad ppr64_reg_byte i = ptext (case i of { 0 -> sLit "%al"; 1 -> sLit "%bl"; 2 -> sLit "%cl"; 3 -> sLit "%dl"; 4 -> sLit "%sil"; 5 -> sLit "%dil"; -- new 8-bit regs! 6 -> sLit "%bpl"; 7 -> sLit "%spl"; 8 -> sLit "%r8b"; 9 -> sLit "%r9b"; 10 -> sLit "%r10b"; 11 -> sLit "%r11b"; 12 -> sLit "%r12b"; 13 -> sLit "%r13b"; 14 -> sLit "%r14b"; 15 -> sLit "%r15b"; _ -> sLit "very naughty x86_64 byte register" }) ppr64_reg_word i = ptext (case i of { 0 -> sLit "%ax"; 1 -> sLit "%bx"; 2 -> sLit "%cx"; 3 -> sLit "%dx"; 4 -> sLit "%si"; 5 -> sLit "%di"; 6 -> sLit "%bp"; 7 -> sLit "%sp"; 8 -> sLit "%r8w"; 9 -> sLit "%r9w"; 10 -> sLit "%r10w"; 11 -> sLit "%r11w"; 12 -> sLit "%r12w"; 13 -> sLit "%r13w"; 14 -> sLit "%r14w"; 15 -> sLit "%r15w"; _ -> sLit "very naughty x86_64 word register" }) ppr64_reg_long i = ptext (case i of { 0 -> sLit "%eax"; 1 -> sLit "%ebx"; 2 -> sLit "%ecx"; 3 -> sLit "%edx"; 4 -> sLit "%esi"; 5 -> sLit "%edi"; 6 -> sLit "%ebp"; 7 -> sLit "%esp"; 8 -> sLit "%r8d"; 9 -> sLit "%r9d"; 10 -> sLit "%r10d"; 11 -> sLit "%r11d"; 12 -> sLit "%r12d"; 13 -> sLit "%r13d"; 14 -> sLit "%r14d"; 15 -> sLit "%r15d"; _ -> sLit "very naughty x86_64 register" }) ppr64_reg_quad i = ptext (case i of { 0 -> sLit "%rax"; 1 -> sLit "%rbx"; 2 -> sLit "%rcx"; 3 -> sLit "%rdx"; 4 -> sLit "%rsi"; 5 -> sLit "%rdi"; 6 -> sLit "%rbp"; 7 -> sLit "%rsp"; 8 -> sLit "%r8"; 9 -> sLit "%r9"; 10 -> sLit "%r10"; 11 -> sLit "%r11"; 12 -> sLit "%r12"; 13 -> sLit "%r13"; 14 -> sLit "%r14"; 15 -> sLit "%r15"; _ -> ppr_reg_float i }) ppr_reg_float :: Int -> LitString ppr_reg_float i = case i of 16 -> sLit "%fake0"; 17 -> sLit "%fake1" 18 -> sLit "%fake2"; 19 -> sLit "%fake3" 20 -> sLit "%fake4"; 21 -> sLit "%fake5" 24 -> sLit "%xmm0"; 25 -> sLit "%xmm1" 26 -> sLit "%xmm2"; 27 -> sLit "%xmm3" 28 -> sLit "%xmm4"; 29 -> sLit "%xmm5" 30 -> sLit "%xmm6"; 31 -> sLit "%xmm7" 32 -> sLit "%xmm8"; 33 -> sLit "%xmm9" 34 -> sLit "%xmm10"; 35 -> sLit "%xmm11" 36 -> sLit "%xmm12"; 37 -> sLit "%xmm13" 38 -> sLit "%xmm14"; 39 -> sLit "%xmm15" _ -> sLit "very naughty x86 register" pprSize :: Size -> SDoc pprSize x = ptext (case x of II8 -> sLit "b" II16 -> sLit "w" II32 -> sLit "l" II64 -> sLit "q" FF32 -> sLit "ss" -- "scalar single-precision float" (SSE2) FF64 -> sLit "sd" -- "scalar double-precision float" (SSE2) FF80 -> sLit "t" ) pprSize_x87 :: Size -> SDoc pprSize_x87 x = ptext $ case x of FF32 -> sLit "s" FF64 -> sLit "l" FF80 -> sLit "t" _ -> panic "X86.Ppr.pprSize_x87" pprCond :: Cond -> SDoc pprCond c = ptext (case c of { GEU -> sLit "ae"; LU -> sLit "b"; EQQ -> sLit "e"; GTT -> sLit "g"; GE -> sLit "ge"; GU -> sLit "a"; LTT -> sLit "l"; LE -> sLit "le"; LEU -> sLit "be"; NE -> sLit "ne"; NEG -> sLit "s"; POS -> sLit "ns"; CARRY -> sLit "c"; OFLO -> sLit "o"; PARITY -> sLit "p"; NOTPARITY -> sLit "np"; ALWAYS -> sLit "mp"}) pprImm :: Imm -> SDoc pprImm (ImmInt i) = int i pprImm (ImmInteger i) = integer i pprImm (ImmCLbl l) = ppr l pprImm (ImmIndex l i) = ppr l <> char '+' <> int i pprImm (ImmLit s) = s pprImm (ImmFloat _) = ptext (sLit "naughty float immediate") pprImm (ImmDouble _) = ptext (sLit "naughty double immediate") pprImm (ImmConstantSum a b) = pprImm a <> char '+' <> pprImm b pprImm (ImmConstantDiff a b) = pprImm a <> char '-' <> lparen <> pprImm b <> rparen pprAddr :: AddrMode -> SDoc pprAddr (ImmAddr imm off) = let pp_imm = pprImm imm in if (off == 0) then pp_imm else if (off < 0) then pp_imm <> int off else pp_imm <> char '+' <> int off pprAddr (AddrBaseIndex base index displacement) = sdocWithPlatform $ \platform -> let pp_disp = ppr_disp displacement pp_off p = pp_disp <> char '(' <> p <> char ')' pp_reg r = pprReg (archWordSize (target32Bit platform)) r in case (base, index) of (EABaseNone, EAIndexNone) -> pp_disp (EABaseReg b, EAIndexNone) -> pp_off (pp_reg b) (EABaseRip, EAIndexNone) -> pp_off (ptext (sLit "%rip")) (EABaseNone, EAIndex r i) -> pp_off (comma <> pp_reg r <> comma <> int i) (EABaseReg b, EAIndex r i) -> pp_off (pp_reg b <> comma <> pp_reg r <> comma <> int i) _ -> panic "X86.Ppr.pprAddr: no match" where ppr_disp (ImmInt 0) = empty ppr_disp imm = pprImm imm pprSectionHeader :: Section -> SDoc pprSectionHeader seg = sdocWithPlatform $ \platform -> case platformOS platform of OSDarwin | target32Bit platform -> case seg of Text -> ptext (sLit ".text\n\t.align 2") Data -> ptext (sLit ".data\n\t.align 2") ReadOnlyData -> ptext (sLit ".const\n.align 2") RelocatableReadOnlyData -> ptext (sLit ".const_data\n.align 2") UninitialisedData -> ptext (sLit ".data\n\t.align 2") ReadOnlyData16 -> ptext (sLit ".const\n.align 4") OtherSection _ -> panic "X86.Ppr.pprSectionHeader: unknown section" | otherwise -> case seg of Text -> ptext (sLit ".text\n.align 3") Data -> ptext (sLit ".data\n.align 3") ReadOnlyData -> ptext (sLit ".const\n.align 3") RelocatableReadOnlyData -> ptext (sLit ".const_data\n.align 3") UninitialisedData -> ptext (sLit ".data\n\t.align 3") ReadOnlyData16 -> ptext (sLit ".const\n.align 4") OtherSection _ -> panic "PprMach.pprSectionHeader: unknown section" _ | target32Bit platform -> case seg of Text -> ptext (sLit ".text\n\t.align 4,0x90") Data -> ptext (sLit ".data\n\t.align 4") ReadOnlyData -> ptext (sLit ".section .rodata\n\t.align 4") RelocatableReadOnlyData -> ptext (sLit ".section .data\n\t.align 4") UninitialisedData -> ptext (sLit ".section .bss\n\t.align 4") ReadOnlyData16 -> ptext (sLit ".section .rodata\n\t.align 16") OtherSection _ -> panic "X86.Ppr.pprSectionHeader: unknown section" | otherwise -> case seg of Text -> ptext (sLit ".text\n\t.align 8") Data -> ptext (sLit ".data\n\t.align 8") ReadOnlyData -> ptext (sLit ".section .rodata\n\t.align 8") RelocatableReadOnlyData -> ptext (sLit ".section .data\n\t.align 8") UninitialisedData -> ptext (sLit ".section .bss\n\t.align 8") ReadOnlyData16 -> ptext (sLit ".section .rodata.cst16\n\t.align 16") OtherSection _ -> panic "PprMach.pprSectionHeader: unknown section" pprDataItem :: CmmLit -> SDoc pprDataItem lit = sdocWithDynFlags $ \dflags -> pprDataItem' dflags lit pprDataItem' :: DynFlags -> CmmLit -> SDoc pprDataItem' dflags lit = vcat (ppr_item (cmmTypeSize $ cmmLitType dflags lit) lit) where platform = targetPlatform dflags imm = litToImm lit -- These seem to be common: ppr_item II8 _ = [ptext (sLit "\t.byte\t") <> pprImm imm] ppr_item II16 _ = [ptext (sLit "\t.word\t") <> pprImm imm] ppr_item II32 _ = [ptext (sLit "\t.long\t") <> pprImm imm] ppr_item FF32 (CmmFloat r _) = let bs = floatToBytes (fromRational r) in map (\b -> ptext (sLit "\t.byte\t") <> pprImm (ImmInt b)) bs ppr_item FF64 (CmmFloat r _) = let bs = doubleToBytes (fromRational r) in map (\b -> ptext (sLit "\t.byte\t") <> pprImm (ImmInt b)) bs ppr_item II64 _ = case platformOS platform of OSDarwin | target32Bit platform -> case lit of CmmInt x _ -> [ptext (sLit "\t.long\t") <> int (fromIntegral (fromIntegral x :: Word32)), ptext (sLit "\t.long\t") <> int (fromIntegral (fromIntegral (x `shiftR` 32) :: Word32))] _ -> panic "X86.Ppr.ppr_item: no match for II64" | otherwise -> [ptext (sLit "\t.quad\t") <> pprImm imm] _ | target32Bit platform -> [ptext (sLit "\t.quad\t") <> pprImm imm] | otherwise -> -- x86_64: binutils can't handle the R_X86_64_PC64 -- relocation type, which means we can't do -- pc-relative 64-bit addresses. Fortunately we're -- assuming the small memory model, in which all such -- offsets will fit into 32 bits, so we have to stick -- to 32-bit offset fields and modify the RTS -- appropriately -- -- See Note [x86-64-relative] in includes/rts/storage/InfoTables.h -- case lit of -- A relative relocation: CmmLabelDiffOff _ _ _ -> [ptext (sLit "\t.long\t") <> pprImm imm, ptext (sLit "\t.long\t0")] _ -> [ptext (sLit "\t.quad\t") <> pprImm imm] ppr_item _ _ = panic "X86.Ppr.ppr_item: no match" pprInstr :: Instr -> SDoc pprInstr (COMMENT _) = empty -- nuke 'em {- pprInstr (COMMENT s) = ptext (sLit "# ") <> ftext s -} pprInstr (DELTA d) = pprInstr (COMMENT (mkFastString ("\tdelta = " ++ show d))) pprInstr (NEWBLOCK _) = panic "PprMach.pprInstr: NEWBLOCK" pprInstr (LDATA _ _) = panic "PprMach.pprInstr: LDATA" {- pprInstr (SPILL reg slot) = hcat [ ptext (sLit "\tSPILL"), char ' ', pprUserReg reg, comma, ptext (sLit "SLOT") <> parens (int slot)] pprInstr (RELOAD slot reg) = hcat [ ptext (sLit "\tRELOAD"), char ' ', ptext (sLit "SLOT") <> parens (int slot), comma, pprUserReg reg] -} pprInstr (MOV size src dst) = pprSizeOpOp (sLit "mov") size src dst +pprInstr (CMOV cc size src dst) + = pprCondOpReg (sLit "cmov") size cc src dst + pprInstr (MOVZxL II32 src dst) = pprSizeOpOp (sLit "mov") II32 src dst -- 32-to-64 bit zero extension on x86_64 is accomplished by a simple -- movl. But we represent it as a MOVZxL instruction, because -- the reg alloc would tend to throw away a plain reg-to-reg -- move, and we still want it to do that. pprInstr (MOVZxL sizes src dst) = pprSizeOpOpCoerce (sLit "movz") sizes II32 src dst -- zero-extension only needs to extend to 32 bits: on x86_64, -- the remaining zero-extension to 64 bits is automatic, and the 32-bit -- instruction is shorter. pprInstr (MOVSxL sizes src dst) = sdocWithPlatform $ \platform -> pprSizeOpOpCoerce (sLit "movs") sizes (archWordSize (target32Bit platform)) src dst -- here we do some patching, since the physical registers are only set late -- in the code generation. pprInstr (LEA size (OpAddr (AddrBaseIndex (EABaseReg reg1) (EAIndex reg2 1) (ImmInt 0))) dst@(OpReg reg3)) | reg1 == reg3 = pprSizeOpOp (sLit "add") size (OpReg reg2) dst pprInstr (LEA size (OpAddr (AddrBaseIndex (EABaseReg reg1) (EAIndex reg2 1) (ImmInt 0))) dst@(OpReg reg3)) | reg2 == reg3 = pprSizeOpOp (sLit "add") size (OpReg reg1) dst pprInstr (LEA size (OpAddr (AddrBaseIndex (EABaseReg reg1) EAIndexNone displ)) dst@(OpReg reg3)) | reg1 == reg3 = pprInstr (ADD size (OpImm displ) dst) pprInstr (LEA size src dst) = pprSizeOpOp (sLit "lea") size src dst pprInstr (ADD size (OpImm (ImmInt (-1))) dst) = pprSizeOp (sLit "dec") size dst pprInstr (ADD size (OpImm (ImmInt 1)) dst) = pprSizeOp (sLit "inc") size dst pprInstr (ADD size src dst) = pprSizeOpOp (sLit "add") size src dst pprInstr (ADC size src dst) = pprSizeOpOp (sLit "adc") size src dst pprInstr (SUB size src dst) = pprSizeOpOp (sLit "sub") size src dst pprInstr (IMUL size op1 op2) = pprSizeOpOp (sLit "imul") size op1 op2 pprInstr (ADD_CC size src dst) = pprSizeOpOp (sLit "add") size src dst {- A hack. The Intel documentation says that "The two and three operand forms [of IMUL] may also be used with unsigned operands because the lower half of the product is the same regardless if (sic) the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero." So there. -} pprInstr (AND size src dst) = pprSizeOpOp (sLit "and") size src dst pprInstr (OR size src dst) = pprSizeOpOp (sLit "or") size src dst pprInstr (XOR FF32 src dst) = pprOpOp (sLit "xorps") FF32 src dst pprInstr (XOR FF64 src dst) = pprOpOp (sLit "xorpd") FF64 src dst pprInstr (XOR size src dst) = pprSizeOpOp (sLit "xor") size src dst pprInstr (POPCNT size src dst) = pprOpOp (sLit "popcnt") size src (OpReg dst) pprInstr (BSF size src dst) = pprOpOp (sLit "bsf") size src (OpReg dst) pprInstr (BSR size src dst) = pprOpOp (sLit "bsr") size src (OpReg dst) pprInstr (PREFETCH NTA size src ) = pprSizeOp_ (sLit "prefetchnta") size src pprInstr (PREFETCH Lvl0 size src) = pprSizeOp_ (sLit "prefetcht0") size src pprInstr (PREFETCH Lvl1 size src) = pprSizeOp_ (sLit "prefetcht1") size src pprInstr (PREFETCH Lvl2 size src) = pprSizeOp_ (sLit "prefetcht2") size src pprInstr (NOT size op) = pprSizeOp (sLit "not") size op pprInstr (BSWAP size op) = pprSizeOp (sLit "bswap") size (OpReg op) pprInstr (NEGI size op) = pprSizeOp (sLit "neg") size op pprInstr (SHL size src dst) = pprShift (sLit "shl") size src dst pprInstr (SAR size src dst) = pprShift (sLit "sar") size src dst pprInstr (SHR size src dst) = pprShift (sLit "shr") size src dst pprInstr (BT size imm src) = pprSizeImmOp (sLit "bt") size imm src pprInstr (CMP size src dst) | is_float size = pprSizeOpOp (sLit "ucomi") size src dst -- SSE2 | otherwise = pprSizeOpOp (sLit "cmp") size src dst where -- This predicate is needed here and nowhere else is_float FF32 = True is_float FF64 = True is_float FF80 = True is_float _ = False pprInstr (TEST size src dst) = pprSizeOpOp (sLit "test") size src dst pprInstr (PUSH size op) = pprSizeOp (sLit "push") size op pprInstr (POP size op) = pprSizeOp (sLit "pop") size op -- both unused (SDM): -- pprInstr PUSHA = ptext (sLit "\tpushal") -- pprInstr POPA = ptext (sLit "\tpopal") pprInstr NOP = ptext (sLit "\tnop") pprInstr (CLTD II32) = ptext (sLit "\tcltd") pprInstr (CLTD II64) = ptext (sLit "\tcqto") pprInstr (SETCC cond op) = pprCondInstr (sLit "set") cond (pprOperand II8 op) pprInstr (JXX cond blockid) = pprCondInstr (sLit "j") cond (ppr lab) where lab = mkAsmTempLabel (getUnique blockid) pprInstr (JXX_GBL cond imm) = pprCondInstr (sLit "j") cond (pprImm imm) pprInstr (JMP (OpImm imm) _) = ptext (sLit "\tjmp ") <> pprImm imm pprInstr (JMP op _) = sdocWithPlatform $ \platform -> ptext (sLit "\tjmp *") <> pprOperand (archWordSize (target32Bit platform)) op pprInstr (JMP_TBL op _ _ _) = pprInstr (JMP op []) pprInstr (CALL (Left imm) _) = ptext (sLit "\tcall ") <> pprImm imm pprInstr (CALL (Right reg) _) = sdocWithPlatform $ \platform -> ptext (sLit "\tcall *") <> pprReg (archWordSize (target32Bit platform)) reg pprInstr (IDIV sz op) = pprSizeOp (sLit "idiv") sz op pprInstr (DIV sz op) = pprSizeOp (sLit "div") sz op pprInstr (IMUL2 sz op) = pprSizeOp (sLit "imul") sz op -- x86_64 only pprInstr (MUL size op1 op2) = pprSizeOpOp (sLit "mul") size op1 op2 pprInstr (MUL2 size op) = pprSizeOp (sLit "mul") size op pprInstr (FDIV size op1 op2) = pprSizeOpOp (sLit "div") size op1 op2 pprInstr (CVTSS2SD from to) = pprRegReg (sLit "cvtss2sd") from to pprInstr (CVTSD2SS from to) = pprRegReg (sLit "cvtsd2ss") from to pprInstr (CVTTSS2SIQ sz from to) = pprSizeSizeOpReg (sLit "cvttss2si") FF32 sz from to pprInstr (CVTTSD2SIQ sz from to) = pprSizeSizeOpReg (sLit "cvttsd2si") FF64 sz from to pprInstr (CVTSI2SS sz from to) = pprSizeOpReg (sLit "cvtsi2ss") sz from to pprInstr (CVTSI2SD sz from to) = pprSizeOpReg (sLit "cvtsi2sd") sz from to -- FETCHGOT for PIC on ELF platforms pprInstr (FETCHGOT reg) = vcat [ ptext (sLit "\tcall 1f"), hcat [ ptext (sLit "1:\tpopl\t"), pprReg II32 reg ], hcat [ ptext (sLit "\taddl\t$_GLOBAL_OFFSET_TABLE_+(.-1b), "), pprReg II32 reg ] ] -- FETCHPC for PIC on Darwin/x86 -- get the instruction pointer into a register -- (Terminology note: the IP is called Program Counter on PPC, -- and it's a good thing to use the same name on both platforms) pprInstr (FETCHPC reg) = vcat [ ptext (sLit "\tcall 1f"), hcat [ ptext (sLit "1:\tpopl\t"), pprReg II32 reg ] ] -- ----------------------------------------------------------------------------- -- i386 floating-point -- Simulating a flat register set on the x86 FP stack is tricky. -- you have to free %st(7) before pushing anything on the FP reg stack -- so as to preclude the possibility of a FP stack overflow exception. pprInstr g@(GMOV src dst) | src == dst = empty | otherwise = pprG g (hcat [gtab, gpush src 0, gsemi, gpop dst 1]) -- GLD sz addr dst ==> FLDsz addr ; FSTP (dst+1) pprInstr g@(GLD sz addr dst) = pprG g (hcat [gtab, text "fld", pprSize_x87 sz, gsp, pprAddr addr, gsemi, gpop dst 1]) -- GST sz src addr ==> FLD dst ; FSTPsz addr pprInstr g@(GST sz src addr) | src == fake0 && sz /= FF80 -- fstt instruction doesn't exist = pprG g (hcat [gtab, text "fst", pprSize_x87 sz, gsp, pprAddr addr]) | otherwise = pprG g (hcat [gtab, gpush src 0, gsemi, text "fstp", pprSize_x87 sz, gsp, pprAddr addr]) pprInstr g@(GLDZ dst) = pprG g (hcat [gtab, text "fldz ; ", gpop dst 1]) pprInstr g@(GLD1 dst) = pprG g (hcat [gtab, text "fld1 ; ", gpop dst 1]) pprInstr (GFTOI src dst) = pprInstr (GDTOI src dst) pprInstr g@(GDTOI src dst) = pprG g (vcat [ hcat [gtab, text "subl $8, %esp ; fnstcw 4(%esp)"], hcat [gtab, gpush src 0], hcat [gtab, text "movzwl 4(%esp), ", reg, text " ; orl $0xC00, ", reg], hcat [gtab, text "movl ", reg, text ", 0(%esp) ; fldcw 0(%esp)"], hcat [gtab, text "fistpl 0(%esp)"], hcat [gtab, text "fldcw 4(%esp) ; movl 0(%esp), ", reg], hcat [gtab, text "addl $8, %esp"] ]) where reg = pprReg II32 dst pprInstr (GITOF src dst) = pprInstr (GITOD src dst) pprInstr g@(GITOD src dst) = pprG g (hcat [gtab, text "pushl ", pprReg II32 src, text " ; fildl (%esp) ; ", gpop dst 1, text " ; addl $4,%esp"]) pprInstr g@(GDTOF src dst) = pprG g (vcat [gtab <> gpush src 0, gtab <> text "subl $4,%esp ; fstps (%esp) ; flds (%esp) ; addl $4,%esp ;", gtab <> gpop dst 1]) {- Gruesome swamp follows. If you're unfortunate enough to have ventured this far into the jungle AND you give a Rat's Ass (tm) what's going on, here's the deal. Generate code to do a floating point comparison of src1 and src2, of kind cond, and set the Zero flag if true. The complications are to do with handling NaNs correctly. We want the property that if either argument is NaN, then the result of the comparison is False ... except if we're comparing for inequality, in which case the answer is True. Here's how the general (non-inequality) case works. As an example, consider generating the an equality test: pushl %eax -- we need to mess with this fcomp and pop pushed src1 -- Result of comparison is in FPU Status Register bits -- C3 C2 and C0 fstsw %ax -- Move FPU Status Reg to %ax sahf -- move C3 C2 C0 from %ax to integer flag reg -- now the serious magic begins setpo %ah -- %ah = if comparable(neither arg was NaN) then 1 else 0 sete %al -- %al = if arg1 == arg2 then 1 else 0 andb %ah,%al -- %al &= %ah -- so %al == 1 iff (comparable && same); else it holds 0 decb %al -- %al == 0, ZeroFlag=1 iff (comparable && same); else %al == 0xFF, ZeroFlag=0 -- the zero flag is now set as we desire. popl %eax The special case of inequality differs thusly: setpe %ah -- %ah = if incomparable(either arg was NaN) then 1 else 0 setne %al -- %al = if arg1 /= arg2 then 1 else 0 orb %ah,%al -- %al = if (incomparable || different) then 1 else 0 decb %al -- if (incomparable || different) then (%al == 0, ZF=1) else (%al == 0xFF, ZF=0) -} pprInstr g@(GCMP cond src1 src2) | case cond of { NE -> True; _ -> False } = pprG g (vcat [ hcat [gtab, text "pushl %eax ; ",gpush src1 0], hcat [gtab, text "fcomp ", greg src2 1, text "; fstsw %ax ; sahf ; setpe %ah"], hcat [gtab, text "setne %al ; ", text "orb %ah,%al ; decb %al ; popl %eax"] ]) | otherwise = pprG g (vcat [ hcat [gtab, text "pushl %eax ; ",gpush src1 0], hcat [gtab, text "fcomp ", greg src2 1, text "; fstsw %ax ; sahf ; setpo %ah"], hcat [gtab, text "set", pprCond (fix_FP_cond cond), text " %al ; ", text "andb %ah,%al ; decb %al ; popl %eax"] ]) where {- On the 486, the flags set by FP compare are the unsigned ones! (This looks like a HACK to me. WDP 96/03) -} fix_FP_cond :: Cond -> Cond fix_FP_cond GE = GEU fix_FP_cond GTT = GU fix_FP_cond LTT = LU fix_FP_cond LE = LEU fix_FP_cond EQQ = EQQ fix_FP_cond NE = NE fix_FP_cond _ = panic "X86.Ppr.fix_FP_cond: no match" -- there should be no others pprInstr g@(GABS _ src dst) = pprG g (hcat [gtab, gpush src 0, text " ; fabs ; ", gpop dst 1]) pprInstr g@(GNEG _ src dst) = pprG g (hcat [gtab, gpush src 0, text " ; fchs ; ", gpop dst 1]) pprInstr g@(GSQRT sz src dst) = pprG g (hcat [gtab, gpush src 0, text " ; fsqrt"] $$ hcat [gtab, gcoerceto sz, gpop dst 1]) pprInstr g@(GSIN sz l1 l2 src dst) = pprG g (pprTrigOp "fsin" False l1 l2 src dst sz) pprInstr g@(GCOS sz l1 l2 src dst) = pprG g (pprTrigOp "fcos" False l1 l2 src dst sz) pprInstr g@(GTAN sz l1 l2 src dst) = pprG g (pprTrigOp "fptan" True l1 l2 src dst sz) -- In the translations for GADD, GMUL, GSUB and GDIV, -- the first two cases are mere optimisations. The otherwise clause -- generates correct code under all circumstances. pprInstr g@(GADD _ src1 src2 dst) | src1 == dst = pprG g (text "\t#GADD-xxxcase1" $$ hcat [gtab, gpush src2 0, text " ; faddp %st(0),", greg src1 1]) | src2 == dst = pprG g (text "\t#GADD-xxxcase2" $$ hcat [gtab, gpush src1 0, text " ; faddp %st(0),", greg src2 1]) | otherwise = pprG g (hcat [gtab, gpush src1 0, text " ; fadd ", greg src2 1, text ",%st(0)", gsemi, gpop dst 1]) pprInstr g@(GMUL _ src1 src2 dst) | src1 == dst = pprG g (text "\t#GMUL-xxxcase1" $$ hcat [gtab, gpush src2 0, text " ; fmulp %st(0),", greg src1 1]) | src2 == dst = pprG g (text "\t#GMUL-xxxcase2" $$ hcat [gtab, gpush src1 0, text " ; fmulp %st(0),", greg src2 1]) | otherwise = pprG g (hcat [gtab, gpush src1 0, text " ; fmul ", greg src2 1, text ",%st(0)", gsemi, gpop dst 1]) pprInstr g@(GSUB _ src1 src2 dst) | src1 == dst = pprG g (text "\t#GSUB-xxxcase1" $$ hcat [gtab, gpush src2 0, text " ; fsubrp %st(0),", greg src1 1]) | src2 == dst = pprG g (text "\t#GSUB-xxxcase2" $$ hcat [gtab, gpush src1 0, text " ; fsubp %st(0),", greg src2 1]) | otherwise = pprG g (hcat [gtab, gpush src1 0, text " ; fsub ", greg src2 1, text ",%st(0)", gsemi, gpop dst 1]) pprInstr g@(GDIV _ src1 src2 dst) | src1 == dst = pprG g (text "\t#GDIV-xxxcase1" $$ hcat [gtab, gpush src2 0, text " ; fdivrp %st(0),", greg src1 1]) | src2 == dst = pprG g (text "\t#GDIV-xxxcase2" $$ hcat [gtab, gpush src1 0, text " ; fdivp %st(0),", greg src2 1]) | otherwise = pprG g (hcat [gtab, gpush src1 0, text " ; fdiv ", greg src2 1, text ",%st(0)", gsemi, gpop dst 1]) pprInstr GFREE = vcat [ ptext (sLit "\tffree %st(0) ;ffree %st(1) ;ffree %st(2) ;ffree %st(3)"), ptext (sLit "\tffree %st(4) ;ffree %st(5)") ] -- Atomics pprInstr (LOCK i) = ptext (sLit "\tlock") $$ pprInstr i pprInstr MFENCE = ptext (sLit "\tmfence") pprInstr (XADD size src dst) = pprSizeOpOp (sLit "xadd") size src dst pprInstr (CMPXCHG size src dst) = pprSizeOpOp (sLit "cmpxchg") size src dst pprInstr _ = panic "X86.Ppr.pprInstr: no match" pprTrigOp :: String -> Bool -> CLabel -> CLabel -> Reg -> Reg -> Size -> SDoc pprTrigOp op -- fsin, fcos or fptan isTan -- we need a couple of extra steps if we're doing tan l1 l2 -- internal labels for us to use src dst sz = -- We'll be needing %eax later on hcat [gtab, text "pushl %eax;"] $$ -- tan is going to use an extra space on the FP stack (if isTan then hcat [gtab, text "ffree %st(6)"] else empty) $$ -- First put the value in %st(0) and try to apply the op to it hcat [gpush src 0, text ("; " ++ op)] $$ -- Now look to see if C2 was set (overflow, |value| >= 2^63) hcat [gtab, text "fnstsw %ax"] $$ hcat [gtab, text "test $0x400,%eax"] $$ -- If we were in bounds then jump to the end hcat [gtab, text "je " <> ppr l1] $$ -- Otherwise we need to shrink the value. Start by -- loading pi, doubleing it (by adding it to itself), -- and then swapping pi with the value, so the value we -- want to apply op to is in %st(0) again hcat [gtab, text "ffree %st(7); fldpi"] $$ hcat [gtab, text "fadd %st(0),%st"] $$ hcat [gtab, text "fxch %st(1)"] $$ -- Now we have a loop in which we make the value smaller, -- see if it's small enough, and loop if not (ppr l2 <> char ':') $$ hcat [gtab, text "fprem1"] $$ -- My Debian libc uses fstsw here for the tan code, but I can't -- see any reason why it should need to be different for tan. hcat [gtab, text "fnstsw %ax"] $$ hcat [gtab, text "test $0x400,%eax"] $$ hcat [gtab, text "jne " <> ppr l2] $$ hcat [gtab, text "fstp %st(1)"] $$ hcat [gtab, text op] $$ (ppr l1 <> char ':') $$ -- Pop the 1.0 tan gave us (if isTan then hcat [gtab, text "fstp %st(0)"] else empty) $$ -- Restore %eax hcat [gtab, text "popl %eax;"] $$ -- And finally make the result the right size hcat [gtab, gcoerceto sz, gpop dst 1] -------------------------- -- coerce %st(0) to the specified size gcoerceto :: Size -> SDoc gcoerceto FF64 = empty gcoerceto FF32 = empty --text "subl $4,%esp ; fstps (%esp) ; flds (%esp) ; addl $4,%esp ; " gcoerceto _ = panic "X86.Ppr.gcoerceto: no match" gpush :: Reg -> RegNo -> SDoc gpush reg offset = hcat [text "fld ", greg reg offset] gpop :: Reg -> RegNo -> SDoc gpop reg offset = hcat [text "fstp ", greg reg offset] greg :: Reg -> RegNo -> SDoc greg reg offset = text "%st(" <> int (gregno reg - firstfake+offset) <> char ')' gsemi :: SDoc gsemi = text " ; " gtab :: SDoc gtab = char '\t' gsp :: SDoc gsp = char ' ' gregno :: Reg -> RegNo gregno (RegReal (RealRegSingle i)) = i gregno _ = --pprPanic "gregno" (ppr other) 999 -- bogus; only needed for debug printing pprG :: Instr -> SDoc -> SDoc pprG fake actual = (char '#' <> pprGInstr fake) $$ actual pprGInstr :: Instr -> SDoc pprGInstr (GMOV src dst) = pprSizeRegReg (sLit "gmov") FF64 src dst pprGInstr (GLD sz src dst) = pprSizeAddrReg (sLit "gld") sz src dst pprGInstr (GST sz src dst) = pprSizeRegAddr (sLit "gst") sz src dst pprGInstr (GLDZ dst) = pprSizeReg (sLit "gldz") FF64 dst pprGInstr (GLD1 dst) = pprSizeReg (sLit "gld1") FF64 dst pprGInstr (GFTOI src dst) = pprSizeSizeRegReg (sLit "gftoi") FF32 II32 src dst pprGInstr (GDTOI src dst) = pprSizeSizeRegReg (sLit "gdtoi") FF64 II32 src dst pprGInstr (GITOF src dst) = pprSizeSizeRegReg (sLit "gitof") II32 FF32 src dst pprGInstr (GITOD src dst) = pprSizeSizeRegReg (sLit "gitod") II32 FF64 src dst pprGInstr (GDTOF src dst) = pprSizeSizeRegReg (sLit "gdtof") FF64 FF32 src dst pprGInstr (GCMP co src dst) = pprCondRegReg (sLit "gcmp_") FF64 co src dst pprGInstr (GABS sz src dst) = pprSizeRegReg (sLit "gabs") sz src dst pprGInstr (GNEG sz src dst) = pprSizeRegReg (sLit "gneg") sz src dst pprGInstr (GSQRT sz src dst) = pprSizeRegReg (sLit "gsqrt") sz src dst pprGInstr (GSIN sz _ _ src dst) = pprSizeRegReg (sLit "gsin") sz src dst pprGInstr (GCOS sz _ _ src dst) = pprSizeRegReg (sLit "gcos") sz src dst pprGInstr (GTAN sz _ _ src dst) = pprSizeRegReg (sLit "gtan") sz src dst pprGInstr (GADD sz src1 src2 dst) = pprSizeRegRegReg (sLit "gadd") sz src1 src2 dst pprGInstr (GSUB sz src1 src2 dst) = pprSizeRegRegReg (sLit "gsub") sz src1 src2 dst pprGInstr (GMUL sz src1 src2 dst) = pprSizeRegRegReg (sLit "gmul") sz src1 src2 dst pprGInstr (GDIV sz src1 src2 dst) = pprSizeRegRegReg (sLit "gdiv") sz src1 src2 dst pprGInstr _ = panic "X86.Ppr.pprGInstr: no match" pprDollImm :: Imm -> SDoc pprDollImm i = ptext (sLit "$") <> pprImm i pprOperand :: Size -> Operand -> SDoc pprOperand s (OpReg r) = pprReg s r pprOperand _ (OpImm i) = pprDollImm i pprOperand _ (OpAddr ea) = pprAddr ea pprMnemonic_ :: LitString -> SDoc pprMnemonic_ name = char '\t' <> ptext name <> space pprMnemonic :: LitString -> Size -> SDoc pprMnemonic name size = char '\t' <> ptext name <> pprSize size <> space pprSizeImmOp :: LitString -> Size -> Imm -> Operand -> SDoc pprSizeImmOp name size imm op1 = hcat [ pprMnemonic name size, char '$', pprImm imm, comma, pprOperand size op1 ] pprSizeOp_ :: LitString -> Size -> Operand -> SDoc pprSizeOp_ name size op1 = hcat [ pprMnemonic_ name , pprOperand size op1 ] pprSizeOp :: LitString -> Size -> Operand -> SDoc pprSizeOp name size op1 = hcat [ pprMnemonic name size, pprOperand size op1 ] pprSizeOpOp :: LitString -> Size -> Operand -> Operand -> SDoc pprSizeOpOp name size op1 op2 = hcat [ pprMnemonic name size, pprOperand size op1, comma, pprOperand size op2 ] pprOpOp :: LitString -> Size -> Operand -> Operand -> SDoc pprOpOp name size op1 op2 = hcat [ pprMnemonic_ name, pprOperand size op1, comma, pprOperand size op2 ] pprSizeReg :: LitString -> Size -> Reg -> SDoc pprSizeReg name size reg1 = hcat [ pprMnemonic name size, pprReg size reg1 ] pprSizeRegReg :: LitString -> Size -> Reg -> Reg -> SDoc pprSizeRegReg name size reg1 reg2 = hcat [ pprMnemonic name size, pprReg size reg1, comma, pprReg size reg2 ] pprRegReg :: LitString -> Reg -> Reg -> SDoc pprRegReg name reg1 reg2 = sdocWithPlatform $ \platform -> hcat [ pprMnemonic_ name, pprReg (archWordSize (target32Bit platform)) reg1, comma, pprReg (archWordSize (target32Bit platform)) reg2 ] pprSizeOpReg :: LitString -> Size -> Operand -> Reg -> SDoc pprSizeOpReg name size op1 reg2 = sdocWithPlatform $ \platform -> hcat [ pprMnemonic name size, pprOperand size op1, comma, pprReg (archWordSize (target32Bit platform)) reg2 ] +pprCondOpReg :: LitString -> Size -> Cond -> Operand -> Reg -> SDoc +pprCondOpReg name size cond op1 reg2 + = hcat [ + char '\t', + ptext name, + pprCond cond, + space, + pprOperand size op1, + comma, + pprReg size reg2 + ] + pprCondRegReg :: LitString -> Size -> Cond -> Reg -> Reg -> SDoc pprCondRegReg name size cond reg1 reg2 = hcat [ char '\t', ptext name, pprCond cond, space, pprReg size reg1, comma, pprReg size reg2 ] pprSizeSizeRegReg :: LitString -> Size -> Size -> Reg -> Reg -> SDoc pprSizeSizeRegReg name size1 size2 reg1 reg2 = hcat [ char '\t', ptext name, pprSize size1, pprSize size2, space, pprReg size1 reg1, comma, pprReg size2 reg2 ] pprSizeSizeOpReg :: LitString -> Size -> Size -> Operand -> Reg -> SDoc pprSizeSizeOpReg name size1 size2 op1 reg2 = hcat [ pprMnemonic name size2, pprOperand size1 op1, comma, pprReg size2 reg2 ] pprSizeRegRegReg :: LitString -> Size -> Reg -> Reg -> Reg -> SDoc pprSizeRegRegReg name size reg1 reg2 reg3 = hcat [ pprMnemonic name size, pprReg size reg1, comma, pprReg size reg2, comma, pprReg size reg3 ] pprSizeAddrReg :: LitString -> Size -> AddrMode -> Reg -> SDoc pprSizeAddrReg name size op dst = hcat [ pprMnemonic name size, pprAddr op, comma, pprReg size dst ] pprSizeRegAddr :: LitString -> Size -> Reg -> AddrMode -> SDoc pprSizeRegAddr name size src op = hcat [ pprMnemonic name size, pprReg size src, comma, pprAddr op ] pprShift :: LitString -> Size -> Operand -> Operand -> SDoc pprShift name size src dest = hcat [ pprMnemonic name size, pprOperand II8 src, -- src is 8-bit sized comma, pprOperand size dest ] pprSizeOpOpCoerce :: LitString -> Size -> Size -> Operand -> Operand -> SDoc pprSizeOpOpCoerce name size1 size2 op1 op2 = hcat [ char '\t', ptext name, pprSize size1, pprSize size2, space, pprOperand size1 op1, comma, pprOperand size2 op2 ] pprCondInstr :: LitString -> Cond -> SDoc -> SDoc pprCondInstr name cond arg = hcat [ char '\t', ptext name, pprCond cond, space, arg]